//==========================================================================
// Copyright (c) 2000-2008,  Elastos, Inc.  All Rights Reserved.
//==========================================================================
/*  Copyright ?2002-2003 Intel Corp.
    Bulverde-Mainstone Header File
*/
#ifndef __BVD1BD_H__
#define __BVD1BD_H__

#include "bvd1.h"
#include "bcr.h"
#include "memdefs.h"			// Reserved memory addresses
#include "BLRBits.h"

    //
    // Mainstone: (on PDC): nCS0: Boot FLASH (32MB)
    //
    #define BOOT_FLASH_BASE_PHYSICAL            0x00000000
    #ifdef MMXIP_MEMMAP
    #define BOOT_FLASH_BASE_C_VIRTUAL           0x80000000
    #else
    #define BOOT_FLASH_BASE_C_VIRTUAL           0x98C00000
    #endif //MMXIP_MEMMAP
    #define BOOT_FLASH_BASE_U_VIRTUAL           (BOOT_FLASH_BASE_C_VIRTUAL + CACHED_TO_UNCACHED_OFFSET)

    //
    // Mainstone: nCS1: Secondary FLASH (32MB)
    //
    #define SECONDARY_FLASH_BASE_PHYSICAL       0x04000000
    #ifdef MMXIP_MEMMAP
    #define SECONDARY_FLASH_BASE_C_VIRTUAL      0x82000000
    #else
    #define SECONDARY_FLASH_BASE_C_VIRTUAL      0x96C00000
    #endif //MMXIP_MEMMAP
    #define SECONDARY_FLASH_BASE_U_VIRTUAL      (APP_FLASH_BASE_C_VIRTUAL + CACHED_TO_UNCACHED_OFFSET)

    //
    // Mainstone: nCS2: Board-Level Registers (FPGA)
    //
    #define FPGA_REGS_BASE_PHYSICAL             0x08000000
    #define FPGA_REGS_BASE_C_VIRTUAL            0x96B00000
    #define FPGA_REGS_BASE_U_VIRTUAL            (FPGA_REGS_BASE_C_VIRTUAL + CACHED_TO_UNCACHED_OFFSET)

    //
    // Mainstone: nCS2 (on PDC): SRAM (2 MB)
    //
    #define SRAM_BASE_PHYSICAL                  0x0A000000
    #define SRAM_BASE_C_VIRTUAL                 0x96900000
    #define SRAM_BASE_U_VIRTUAL                 (SRAM_BASE_C_VIRTUAL + CACHED_TO_UNCACHED_OFFSET)

    //
    // Mainstone: nCS3:  not used, not mapped.  Used as PCMCIA PSKTSEK signal on Mainstone.
    //
    #define CS3_BASE_PHYSICAL                   0x0C000000
    #define CS3_BASE_C_VIRTUAL                  0x96800000
    #define CS3_BASE_U_VIRTUAL                  (CS3_BASE_C_VIRTUAL + CACHED_TO_UNCACHED_OFFSET)

    //
    // Mainstone: nCS4: Ethernet (SMSC 91C111)
    //
    #define SMSC_ETHERNET_BASE_PHYSICAL         0x10000000
    #define SMSC_ETHERNET_BASE_C_VIRTUAL        0x96700000
    #define SMSC_ETHERNET_BASE_U_VIRTUAL        (SMSC_ETHERNET_BASE_C_VIRTUAL + CACHED_TO_UNCACHED_OFFSET)

    //
    // Mainstone: nCS5: eXpansion Board Header
    //
    #define XDC_BASE_PHYSICAL                   0x14000000
    #define XDC_BASE_C_VIRTUAL                  0x96600000
    #define XDC_BASE_U_VIRTUAL                  (XDC_BASE_C_VIRTUAL + CACHED_TO_UNCACHED_OFFSET)


    //
    //  Mainstone: Board Level Registers
    //
    typedef struct
    {
      volatile unsigned long   rsvd0[4];         // 0800_0000 -> 0800_000F
      volatile unsigned long     hex_led;        // 0800_0010 -> 0800_0013
      volatile unsigned long     hex_led2;       // 0800_0014 -> 0800_0017
      volatile unsigned long   rsvd1[10];        // 0800_0018 -> 0800_003F
      volatile unsigned long     disc_blnk_led;  // 0800_0040 -> 0800_0043
      volatile unsigned long   rsvd2[7];         // 0800_0044 -> 0800_005F
      volatile unsigned long     gpsw;           // 0800_0060 -> 0800_0063
      volatile unsigned long   rsvd3[7];         // 0800_0064 -> 0080_007F
      volatile unsigned long     misc_wr;        // 0800_0080 -> 0080_0083
      volatile unsigned long     misc_wr2;       // 0800_0084 -> 0080_0087
      volatile unsigned long   rsvd4[2];         // 0800_0088 -> 0800_008F
      volatile unsigned long     misc_rd;        // 0800_0090 -> 0800_0093
      volatile unsigned long   rsvd5[11];        // 0800_0094 -> 0800_00BF
      volatile unsigned long     int_msk_en;     // 0800_00C0 -> 0800_00C3
      volatile unsigned long   rsvd6[3];         // 0800_00C4 -> 0800_00CF
      volatile unsigned long     int_set_clr;    // 0800_00D0 -> 0800_00D3
      volatile unsigned long   rsvd7[3];         // 0800_00D4 -> 0800_00DF
      volatile unsigned long     pcmcia0_srcr;    // 0800_00E0 -> 0800_00E3
      volatile unsigned long     pcmcia1_srcr;    // 0800_00E4 -> 0800_00E7
    } BLR_REGS, *PBLR_REGS;

// <BELOW ITEMS UNTOUCHED FROM COTULLA>


//
// GEDR Power GPIO bits - write to clear
//
#define GEDR_GPIO0_EDGE_CLR(reg) 	(reg = XLLP_GPIO_BIT_0)
#define GEDR_GPIO1_EDGE_CLR(reg) 	(reg = XLLP_GPIO_BIT_1)

//
// Power GPIO edge trigger macros
//
#define POWER_OFF_RISING_EDGE(reg)      (reg |= XLLP_GPIO_BIT_1)
#define POWER_OFF_FALLING_EDGE(reg)     (reg |= XLLP_GPIO_BIT_1)

//
// USB Cable edge trigger macros
//
#define USBCABLE_RISING_EDGE(reg)      (reg |= XLLP_GPIO_BIT_0)
#define USBCABLE_FALLING_EDGE(reg)     (reg |= XLLP_GPIO_BIT_0)
#define USBCABLE_RISING_EDGE_CLR(reg)  (reg &= ~XLLP_GPIO_BIT_0)
#define USBCABLE_FALLING_EDGE_CLR(reg) (reg &= ~XLLP_GPIO_BIT_0)

//
// Processor Stepping Values
//

#define BULVERDE_CP15_A0_VAL 0x69054110
#define BULVERDE_CP15_A1_VAL 0x69054111
#define BULVERDE_CP15_B0_VAL 0x69054112

#define BULVERDE_JTAG_A0_VAL 0x09265013
#define BULVERDE_JTAG_A1_VAL 0x19265013
#define BULVERDE_JTAG_B0_VAL 0x29265013

#endif
